Flash memory is widely used in consumer electronics products for its non-volatility, reliability, low power consumption, and shock resistance. NOR and NAND flash memories have emerged as the dominant varieties of flash memory. Because of its small cell size and a low cost-per-bit, NAND flash memory is suitable for a high-density data storage medium for consumer devices such as digital cameras and solid-state drives (SSDs). NOR flash has typically been used for code storage and direct execution in portable electronics devices, such as cellular phones and personal digital assistants (PDAs). Moreover, SSDs' superior performance, energy efficiency, and energy proportionality over hard disk drives (HDDs) have catalyzed broad and fast adoption not only in consumer products, but also in datacenter and enterprise products.
In NAND flash memory, a programming (or write) operation has a longer latency compared to a read operation. In addition, old data should be erased prior to programming new data to a NAND cell. An erase operation cannot be selectively performed at a cell level, resulting in even a longer latency than the programming latency. Multi-level cell (MLC) NAND flash memory stores multiple states per NAND cell and multiplies the data storage capacity. For example, three-level cell (TLC) NAND flash memory has a density of 3 bits per cell. However, MLC flash memory further decreases the operation speed due to its complex read/programming/erase operations.
The power consumption of electric devices has become a critical metric along with traditional performance metrics for both data center and consumer electronics products. For mobile devices, the battery life is limited, therefore power usage of the components needs to be carefully monitored and controlled to extend the battery life. In data centers, the raw electrical and cooling cost can be of a significant portion of the total operational cost, so the power consumption of the servers can no longer be a lower priority consideration. In addition, modern data center servers have begun to adopt high performance SSDs such as non-volatile memory express (NVMe) devices. A typical NVMe device includes a high-performance central processing unit (CPU) and large dynamic random-access memories (DRAMs). Such high-performance NVMe device can easily consume 25 W, which is a significant amount of power consumption in a data center configuration.
With the requirement of good energy proportionality, that is, proportionally low power consumption is expected for low utilization of a given device, the power consumption of a device can be dynamically changed according to its utilization and/or user settings. The same principal is directly applicable to devices in the consumer market. Mobile devices, such as smartphones, tablet PCs, and laptop computers, have begun to adopt high performance SSDs, such as Peripheral Component Interconnect Express (PCIe)-based SSDs. Power consumption of a SSD is controlled to be minimal, for example, when a laptop computer is unplugged from a power outlet.
Due to its small cell size, high density, low power and high endurance, modern SSDs commonly utilize NAND flash memory as storage media. NAND flash has asymmetric latency and power consumption characteristics. To hide high latency in programming and erasing due to the asymmetric characteristics of NAND flash memory, multiple NAND operations, also referred to as parallelism, may be executed simultaneously. Examples of the parallelism includes multi-plane, data interleave, and multi-channel operations. Due to the parallelism, modern SSDs including NAND flash memory naturally introduce an operation scheduling problem. In addition, existing memory systems require an application programming interface (API) to control dynamic average power consumption. Examples of such API include running average power limit by INTEL, dynamic voltage frequency scaling (DVFS), and power states.